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june 2010 doc id 13587 rev 12 1/96 1 stm32f103x8 stm32f103xb medium-density performance line ar m-based 32-bit mcu with 64 or 128 kb flash, usb, can, 7 timers , 2 adcs, 9 communication interfaces features core: arm 32-bit cortex?-m3 cpu ? 72 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance at 0 wait state memory access ? single-cycle multiplication and hardware division memories ? 64 or 128 kbytes of flash memory ? 20 kbytes of sram clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr, and programmable voltage detector (pvd) ? 4-to-16 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc ? pll for cpu clock ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers 2 x 12-bit, 1 s a/d converters (up to 16 channels) ? conversion range: 0 to 3.6 v ? dual-sample and hold capability ? temperature sensor dma ? 7-channel dma controller ? peripherals supported: timers, adc, spis, i 2 cs and usarts up to 80 fast i/o ports ? 26/37/51/80 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant debug mode ? serial wire debug (swd) & jtag interfaces 7 timers ? three 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? 16-bit, motor control pwm timer with dead- time generation and emergency stop ? 2 watchdog timers (independent and window) ? systick timer: a 24-bit downcounter up to 9 communication interfaces ? up to 2 x i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 2 spis (18 mbit/s) ? can interface (2.0b active) ? usb 2.0 full-speed interface crc calculation unit, 96-bit unique id packages are ecopack ? table 1. device summary reference part number stm32f103x8 stm32f103c8, stm32f103r8 stm32f103v8, stm32f103t8 stm32f103xb stm32f103rb stm32f103vb, stm32f103cb, stm32f103tb bga100 10 10 mm bga64 5 5 mm vfqfpn48 7 7 mm vfqfpn36 6 6 mm lqfp100 14 14 m lqfp64 10 10 m lqfp48 7 7 m www.st.com
contents stm32f103x8, stm32f103xb 2/96 doc id 13587 rev 12 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 14 2.3.2 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.6 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.8 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.9 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.12 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.13 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.17 universal synchronous/asynchronous receiver transmitter (usart) . . 19 2.3.18 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.21 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 adc (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.23 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
stm32f103x8, stm32f103xb contents doc id 13587 rev 12 3/96 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 37 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 37 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.11 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 57 5.3.12 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.13 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.14 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.15 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.16 can (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.17 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.18 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 87 7 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
contents stm32f103x8, stm32f103xb 4/96 doc id 13587 rev 12 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
stm32f103x8, stm32f103xb list of tables doc id 13587 rev 12 5/96 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 table 3. stm32f103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. medium-density stm32f103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 11. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 table 13. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 42 table 16. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 43 table 17. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. hse 4-16 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 table 23. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 24. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 25. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 26. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 27. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 28. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 30. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 31. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 32. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 33. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 34. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 35. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 36. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 37. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 38. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 39. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 40. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 41. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 42. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 43. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 44. usb: full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
list of tables stm32f103x8, stm32f103xb 6/96 doc id 13587 rev 12 table 45. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 46. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 47. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 48. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 49. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 50. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 77 table 51. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 78 table 52. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 53. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 81 table 54. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 82 table 55. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 83 table 56. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 85 table 57. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 58. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
stm32f103x8, stm32f103xb list of figures doc id 13587 rev 12 7/96 list of figures figure 1. stm32f103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. stm32f103xx performance line lfbga100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. stm32f103xx performance line lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. stm32f103xx performance line lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. stm32f103xx performance line tfbga64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. stm32f103xx performance line lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. stm32f103xx performance line vfqfpn48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. stm32f103xx performance line vfqfpn36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled. . . . . . . . . . . . . . . . . . 41 figure 16. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled . . . . . . . . . . . . . . . . . 41 figure 17. typical current consumption on v bat with rtc on versus temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 18. typical current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 19. typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 20. typical current consumption in standby mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 24. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. standard i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 26. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 figure 27. 5 v tolerant i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 28. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 29. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 30. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 31. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 32. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 33. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 34. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 35. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 36. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 37. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 38. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 74 figure 39. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 75 figure 40. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package outline (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 41. recommended footprint (dimensions in mm) (1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 42. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
list of figures stm32f103x8, stm32f103xb 8/96 doc id 13587 rev 12 figure 43. recommended footprint (dimensions in mm) (1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 44. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 45. recommended pcb design rules (0.80/0.75 mm pitch bga) . . . . . . . . . . . . . . . . . . . . . . 80 figure 46. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 81 figure 47. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 48. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 82 figure 49. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 50. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 83 figure 51. recommended pcb design rules for pads (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . . . . 84 figure 52. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 85 figure 53. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 54. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
stm32f103x8, stm32f103xb introduction doc id 13587 rev 12 9/96 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f103x8 and stm32f103xb medium-density performance line microcontrollers. for more details on the whole stmicroelectronics stm32f103xx family, please refer to section 2.2: full compatib ility throughout the family . the medium-density stm32f103xx datasheet should be read in conjunction with the low-, medium- and high-density stm32f10xxx reference manual . the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com. for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 description the stm32f103xx medium-density performance line family incorporates the high- performance arm cortex?-m3 32-bit risc core operating at a 72 mhz frequency, high- speed embedded memories (flash memory up to 128 kbytes and sram up to 20 kbytes), and an extensive range of en hanced i/os and peri pherals connected to two apb buses. all devices offer two 12-bit adcs, three general purpose 16-bit timers plus one pwm timer, as well as standard and advanced communication interfaces: up to two i 2 cs and spis, three usarts, an usb and a can. the devices operate from a 2.0 to 3.6 v power supply. they are available in both the ?40 to +85 c temperature range and the ?40 to +105 c extended temperature range. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. depe nding on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the stm32f103xx medium-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, pc and gaming peripherals, gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs.
description stm32f103x8, stm32f103xb 10/96 doc id 13587 rev 12 2.1 device overview table 2. stm32f103xx medium-density device features and peripheral counts peripheral stm32f103tx stm32f103cx stm32f103rx stm32f103vx flash - kbytes 64 128 64 128 64 128 64 128 sram - kbytes 20 20 20 20 timers general-purpose 33 3 3 advanced-control 11 1 1 communication spi 12 2 2 i 2 c 12 2 2 usart 23 3 3 usb 11 1 1 can 11 1 1 gpios 26 37 51 80 12-bit synchronized adc number of channels 2 10 channels 2 10 channels 2 16 channels 2 16 channels cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c (see ta bl e 9 ) junction temperature: ?40 to + 125 c (see ta bl e 9 ) packages vfqfpn36 lqfp48, vfqfpn48 lqfp64, tfbga64 lqfp100, lfbga100
stm32f103x8, stm32f103xb description doc id 13587 rev 12 11/96 figure 1. stm32f103xx performance line block diagram 1. t a = ?40 c to +105 c (junction temperature up to 125 c). 2. af = alternate function on i/o port pin. u s bdp/can_tx pa[ 15:0] exti wwdg 12 b it adc1 16af jtdi jtck/ s wclk jtm s / s wdio njtr s t tr s t jtdo nr s t v dd = 2 to 3 .6v 8 0af pb[ 15:0] pc[15:0] ahb2 mo s i,mi s o, s ck,n ss s ram 2x( 8 x16 b it) wakeup gpioa gpiob gpioc f m a x : 72 m hz v ss s cl, s da i2c2 v ref+ gp dma tim2 tim 3 xtal o s c 4-16 mhz xtal 3 2 khz o s c_in o s c_out o s c 3 2_out o s c 3 2_in pll & apb1 : f m a x =24 / 3 6 mhz pclk1 hclk clock managt pclk2 as af as af fl as h 12 8 kb volt. reg. 3 . 3 v to 1. 8 v power b a ck u p i nterf a ce as af tim 4 b us m a trix 64 b it inte rf a ce 20 kb rtc rc 8 mhz cortex-m 3 cpu i bu s d bus p bu s o b l fl as h s ram 512b tr a ce controlle r u s art1 u s art2 s pi2 b xcan 7 ch a nnel s b a ck u p reg 4 ch a nn el s tim1 3 co mpl. ch a nn el s s cl, s da, s mba i2c1 as af rx,tx, ct s , rt s , u s art 3 temp s en s or v ref- pd[15:0] gpiod pe[15:0] gpioe ahb:f m a x =4 8 /72 mhz etr a nd bkin 4 ch a nn el s 4 ch a nn el s 4 ch a nn el s fclk rc 40 khz s t a nd b y iwdg @vbat por / pdr s upply @vdda vdda v ss a @vdda v bat rx,tx, ct s , rt s , s m a rt c a rd as af rx,tx, ct s , rt s , ck, s m a rtc a rd as af apb2 : f m a x =4 8 / 72 mhz nvic s pi1 mo s i,mi s o, s ck,n ss as af 12 b i t adc2 if if if interf a ce @vdda s upervi s ion pvd r s t int @vdd ahb2 apb2 apb 1 awu tamper-rtc @vdd u s b 2.0 f s u s bdm/can_rx s y s tem a i14 3 90d traceclk traced[0: 3 ] as a s s w/jtag tpiu tr a ce/trig ck, s m a rtc a rd as af
description stm32f103x8, stm32f103xb 12/96 doc id 13587 rev 12 figure 2. clock tree 1. when the hsi is used as a pll clock input, the maxi mum system clock frequency t hat can be achieved is 64 mhz. 2. for the usb function to be available, both hse and pll must be enabled, with usbclk running at 48 mhz. 3. to have an adc conversion time of 1 s, apb2 must be at 14 mhz, 28 mhz or 56 mhz. hse osc 4-16 mhz osc_in osc_out osc32_in osc32_out lse osc 32.768 khz hsi rc 8 mhz lsi rc 40 khz to independent watchdog (iwdg) pll x2, x3, x4 pllmul legend: mco clock output main pllxtpre /2 ..., x16 ahb prescaler /1, 2..512 /2 pllclk hsi hse apb1 prescaler /1, 2, 4, 8, 16 adc prescaler /2, 4, 6, 8 adcclk pclk1 hclk pllclk to ahb bus, core, memory and dma usbclk to usb interface to tim2, 3 and 4 usb prescaler /1, 1.5 to adc lse lsi hsi /128 /2 hsi hse peripherals to apb1 peripheral clock enable (13 bits) enable (3 bits) p eripheral clock apb2 prescaler /1, 2, 4, 8, 16 pclk2 to tim1 peripherals to apb2 peripheral clock enable (11 bits) enable (1 bit) peripheral clock 48 mhz 72 mhz max 72 mhz 72 mhz max 36 mhz max to rtc pllsrc sw mco css to cortex system timer /8 clock enable (3 bits) sysclk max rtcclk rtcsel[1:0] tim1clk timxclk iwdgclk sysclk fclk cortex free running clock tim2,3, 4 if (apb1 prescaler =1) x1 else x2 tim1 timer if (apb2 prescaler =1) x1 else x2 hse = high-speed external clock signal hsi = high-speed internal clock signal lsi = low-speed internal clock signal lse = low-speed external clock signal ai14903
stm32f103x8, stm32f103xb description doc id 13587 rev 12 13/96 2.2 full compatibility throughout the family the stm32f103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. in the reference manual, the stm32f103x4 and stm32f103x6 are identified as low-density devices, the stm32f103x8 and stm32f103xb are referred to as medium-density devices, and the stm32f103xc, stm32f103xd and stm32f103xe are referred to as high-density devices. low- and high-density devices are an extension of the stm32f103x8/b devices, they are specified in the stm32f103x4/6 and stm32f103xc/d/e datasheets, respectively. low- density devices feature lower flash memory and ram capacities, less timers and peripherals. high-density devices have higher flash memory and ram capacities, and additional peripherals like sdio, fsmc, i 2 s and dac, while remaini ng fully compatible with the other members of the stm32f103xx family. the stm32f103x4, stm32f103x6, stm32f103xc, stm32f103xd and stm32f103xe are a drop-in replacement for stm32f103x8/b medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. moreover, the stm32f103xx performance line fam ily is fully compatible with all existing stm32f101xx access line and stm32f102xx usb access line devices. table 3. stm32f103xx family pinout low-density devices medium-density devices high-density devices 16 kb flash 32 kb flash (1) 1. for orderable part numbers that do not show the a inte rnal code after the temperature range code (6 or 7), the reference datasheet for electric al characteristics is that of the stm32f103x8/b medium-density devices. 64 kb flash 128 kb flash 256 kb flash 384 kb flash 512 kb flash 6 kb ram 10 kb ram 20 kb ram 20 kb ram 48 kb ram 64 kb ram 64 kb ram 144 5 usarts 4 16-bit timers, 2 basic timers 3 spis, 2 i 2 ss, 2 i2cs usb, can, 2 pwm timers 3 adcs, 2 dacs, 1 sdio fsmc (100 and 144 pins) 100 3 usarts 3 16-bit timers 2 spis, 2 i 2 cs, usb, can, 1 pwm timer 2 adcs 64 2 usarts 2 16-bit timers 1 spi, 1 i 2 c, usb, can, 1 pwm timer 2 adcs 48 36
description stm32f103x8, stm32f103xb 14/96 doc id 13587 rev 12 2.3 overview 2.3.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f103xx performance line family having an embedded arm core, is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 2.3.2 embedded flash memory 64 or 128 kbytes of embedded flash is available for storing programs and data. 2.3.3 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.3.4 embedded sram twenty kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. 2.3.5 nested vectored interrupt controller (nvic) the stm32f103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low-latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead
stm32f103x8, stm32f103xb description doc id 13587 rev 12 15/96 this hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 external interrupt /event controller (exti) the external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cl ock period. up to 80 gp ios can be connected to the 16 external interrupt lines. 2.3.7 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-16 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resonator or oscillator). several prescalers allow the configurati on of the ahb frequenc y, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum frequency of the ahb and the high-speed apb domains is 72 mhz. the maximum allowed frequency of the low-speed apb domain is 36 mhz. see figure 2 for details on the clock tree. 2.3.8 boot modes at startup, boot pins are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. for further details please refer to an2606. 2.3.9 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.8 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 13: power supply scheme . 2.3.10 power supply supervisor the device has an integrated power-on reset (por)/power-down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains
description stm32f103x8, stm32f103xb 16/96 doc id 13587 rev 12 in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to table 11: embedded reset and power control block characteristics for the values of v por/pdr and v pvd . 2.3.11 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop mode power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. 2.3.12 low-power modes the stm32f103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode the stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm or the usb wakeup. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode.
stm32f103x8, stm32f103xb description doc id 13587 rev 12 17/96 2.3.13 dma the flexible 7-channel general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose and advanced-control timers timx and adc. 2.3.14 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are ten 16-bit registers used to store 20 bytes of user application data when v dd power is not present. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocke d by a 32.768 khz external crysta l, resonator or oscillator, the internal low-power rc oscillator or the hi gh-speed external cloc k divided by 128. the internal low-power rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural crystal deviation. the rtc features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. 2.3.15 timers and watchdogs the medium-density stm32f103xx performance line devices include an advanced-control timer, three general-purpose timers, two watchdog timers and a systick timer. ta bl e 4 compares the features of the advanced-control and general-purpose timers. table 4. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim1 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s tim2, tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o
description stm32f103x8, stm32f103xb 18/96 doc id 13587 rev 12 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on 6 channels. it has complementary pwm outputs with programmable inserted dead-times. it can also be seen as a complete general-purpose timer. the 4 independent channels can be used for input capture output compare pwm generation (edge- or center-aligned modes) one-pulse mode output if configured as a general-purpose 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switch driven by these outputs. many features are shared with those of the general-purpose tim timers which have the same architecture. the advanced-control timer can therefore work together with the tim timers via the timer link feature for synchronization or event chaining. general-purpose timers (timx) there are up to three synchronizable general-purpose timers embedded in the stm32f103xx performance line devices. these timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the general-purpose timers can work together with the advanced-control timer via the timer link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. they all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently of the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downc ounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode.
stm32f103x8, stm32f103xb description doc id 13587 rev 12 19/96 systick timer this timer is dedicated for os, but could al so be used as a standard downcounter. it features: a 24-bit downcounter autoreload capability maskable system interrupt generation when the counter reaches 0 programmable clock source 2.3.16 i2c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. 2.3.17 universal sy nchronous/asynchronous receiver transmitter (usart) one of the usart interfaces is able to communicate at speeds of up to 4.5 mbit/s. the other available interfaces communicate at up to 2.25 mbit/s. they provide hardware management of the cts and rts signals, irda sir endec support, are iso 7816 compliant and have lin master/slave capability. all usart interfaces can be served by the dma controller. 2.3.18 serial perip heral interface (spi) up to two spis are able to communicate up to 18 mbits/s in slave and master modes in full- duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. both spis can be served by the dma controller. 2.3.19 controller area network (can) the can is compliant with specifications 2.0a and b (active) with a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 2.3.20 universal serial bus (usb) the stm32f103xx performance line embeds a usb device peripheral compatible with the usb full-speed 12 mbs. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator).
description stm32f103x8, stm32f103xb 20/96 doc id 13587 rev 12 2.3.21 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current- capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. i/os on apb2 with up to 18 mhz toggling speed 2.3.22 adc (analog-to -digital converter) two 12-bit analog-to-digital converters are embedded into stm32f103xx performance line devices and each adc shares up to 16 external channels, performing conversions in single- shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold single shunt the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) and the advanced-control timer (tim1) can be internally connected to the adc start trigger, injection trigger, and dma trigger respectively, to allow the application to synchronize a/d conversion and timers. 2.3.23 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc12_in16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.24 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded. and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp.
stm32f103x8, stm32f103xb pinouts and pin description doc id 13587 rev 12 21/96 3 pinouts and pin description figure 3. stm32f103xx performance line lfbga100 ballout ai16001c pe10 pc14- osc32_in pc5 pa5 pc3 pb4 pe15 pb2 pc4 pa4 h pe14 pe11 pe7 d pd4 pd3 pb8 pe3 c pd0 pc12 pe5 pb5 pc0 pe2 b pc11 pd2 pc15- osc32_out pb7 pb6 a 8 7 6 5 4 3 2 1 v ss_5 osc_in osc_out v dd_5 g f e pc1 v ref? pc13- tamper-rtc pb9 pa15 pb3 pe4 pe1 pe0 v ss_1 pd1 pe6 nrst pc2 v ss_3 v ss_4 nc v dd_3 v dd_4 pb15 v bat pd5 pd6 boot0 pd7 v ss_2 v ssa pa1 v dd_2 v dd_1 pb14 pa0-wkup 10 9 k j pd10 pd11 pa8 pa9 pa10 pa11 pa12 pc10 pa13 pa14 pc9 pc7 pc6 pd15 pc8 pd14 pe12 pb1 pa7 pb11 pe8 pb0 pa6 pb10 pe13 pe9 v dda pb13 v ref+ pa3 pb12 pa2 pd8 pd9 pd13 pd12
pinouts and pin description stm32f103x8, stm32f103xb 22/96 doc id 13587 rev 12 figure 4. stm32f103xx performance line lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 ai14391 lqfp100
stm32f103x8, stm32f103xb pinouts and pin description doc id 13587 rev 12 23/96 figure 5. stm32f103xx performance line lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14392
pinouts and pin description stm32f103x8, stm32f103xb 24/96 doc id 13587 rev 12 figure 6. stm32f103xx performance line tfbga64 ballout ai15494 pb2 pc14- osc32_in pa7 pa4 pa2 pa15 pb11 pb1 pa6 pa3 h pb10 pc5 pc4 d pa8 pa9 boot0 pb8 c pc9 pa11 pb6 pc12 v dda pb9 b pa12 pc10 pc15- osc32_out pb3 pd2 a 8 7 6 5 4 3 2 1 v ss_4 osc_in osc_out v dd_4 g f e pc2 v ref+ pc13- tamper-rtc pb4 pa13 pa14 pb7 pb5 v ss_3 pc7 pc8 pc0 nrst pc1 pb0 pa5 pb14 v dd_2 v dd_3 pb13 v bat pc11 pa10 v ss_2 v ss_1 pc6 v ssa pa1 v dd_1 pb15 pb12 pa0-wkup
stm32f103x8, stm32f103xb pinouts and pin description doc id 13587 rev 12 25/96 figure 7. stm32f103xx performance line lqfp48 pinout figure 8. stm32f103xx performance line vfqfpn48 pinout 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pb15 pb14 pb13 pb12 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0-osc_in pd1-osc_out nrst vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa 1 5 pa 1 4 lqfp48 ai14393b ai18300 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0-osc_in pd1-osc_out nrst vssa vdda pa0-wkup pa 1 pa 2 vdd_2 vss_2 pa13 pa12 pa11 pa10 pa 9 pa 8 pb15 pb14 pb13 pb12 48 vfqfpn48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12
pinouts and pin description stm32f103x8, stm32f103xb 26/96 doc id 13587 rev 12 figure 9. stm32f103xx performance line vfqfpn36 pinout v ss_3 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 36 35 34 33 32 31 30 29 28 v dd_3 1 27 v dd_2 osc_in/pd0 2 26 v ss_2 osc_out/pd1 3 25 pa13 nrst 4 qfn36 24 pa12 v ssa 5 23 pa11 v dda 6 22 pa10 pa0-wkup 7 21 pa 9 pa 1 8 20 pa 8 pa 2 9 19 v dd_1 10 11 12 13 14 15 16 17 18 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 v ss_1 ai14654
stm32f103x8, stm32f103xb pinouts and pin description doc id 13587 rev 12 27/96 table 5. medium-density stm32f103xx pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga100 lqfp48/vfqfpn48 tfbga64 lqfp64 lqfp100 vfqfpn36 default remap a3 - - 1 - pe2 i/o ft pe2 traceck b3 - - 2 - pe3 i/o ft pe3 traced0 c3 - - 3 - pe4 i/o ft pe4 traced1 d3 - - 4 - pe5 i/o ft pe5 traced2 e3 - - 5 - pe6 i/o ft pe6 traced3 b2 1 b2 1 6 - v bat sv bat a2 2 a2 2 7 - pc13-tamper- rtc (5) i/o pc13 (6) tamper-rtc a1 3 a1 3 8 - pc14-osc32_in (5) i/o pc14 (6) osc32_in b1 4 b1 4 9 - pc15- osc32_out (5) i/o pc15 (6) osc32_out c2---10- v ss_5 sv ss_5 d2---11- v dd_5 sv dd_5 c1 5 c1 5 12 2 osc_in i osc_in d1 6 d1 6 13 3 osc_out o osc_out e1 7 e1 7 14 4 nrst i/o nrst f1 - e3 8 15 - pc0 i/o pc0 adc12_in10 f2 - e2 9 16 - pc1 i/o pc1 adc12_in11 e2 - f2 10 17 - pc2 i/o pc2 adc12_in12 f3 - - (7) 11 18 - pc3 i/o pc3 adc12_in13 g1 8 f1 12 19 5 v ssa sv ssa h1---20- v ref- sv ref- j1 - g1 (7) -21- v ref+ sv ref+ k1 9 h1 13 22 6 v dda sv dda g2 10 g2 14 23 7 pa0-wkup i/o pa0 wkup/ usart2_cts (8) / adc12_in0/ tim2_ch1_etr (8) h2 11 h2 15 24 8 pa1 i/o pa1 usart2_rts (8) / adc12_in1/ tim2_ch2 (8)
pinouts and pin description stm32f103x8, stm32f103xb 28/96 doc id 13587 rev 12 j2 12 f3 16 25 9 pa2 i/o pa2 usart2_tx (8) / adc12_in2/ tim2_ch3 (8) k2 13 g3 17 26 10 pa3 i/o pa3 usart2_rx (8) / adc12_in3/ tim2_ch4 (8) e4 - c2 18 27 - v ss_4 sv ss_4 f4 - d2 19 28 - v dd_4 sv dd_4 g3 14 h3 20 29 11 pa4 i/o pa4 spi1_nss (8) / usart2_ck (8) / adc12_in4 h3 15 f4 21 30 12 pa5 i/o pa5 spi1_sck (8) / adc12_in5 j3 16 g4 22 31 13 pa6 i/o pa6 spi1_miso (8) / adc12_in6/ tim3_ch1 (8) tim1_bkin k3 17 h4 23 32 14 pa7 i/o pa7 spi1_mosi (8) / adc12_in7/ tim3_ch2 (8) tim1_ch1n g4 - h5 24 33 pc4 i/o pc4 adc12_in14 h4 - h6 25 34 pc5 i/o pc5 adc12_in15 j4 18 f5 26 35 15 pb0 i/o pb0 adc12_in8/ tim3_ch3 (8) tim1_ch2n k4 19 g5 27 36 16 pb1 i/o pb1 adc12_in9/ tim3_ch4 (8) tim1_ch3n g5 20 g6 28 37 17 pb2 i/o ft pb2/boot1 h5 - - - 38 - pe7 i/o ft pe7 tim1_etr j5 - - - 39 - pe8 i/o ft pe8 tim1_ch1n k5 - - - 40 - pe9 i/o ft pe9 tim1_ch1 g6 - - - 41 - pe10 i/o ft pe10 tim1_ch2n h6 - - - 42 - pe11 i/o ft pe11 tim1_ch2 j6 - - - 43 - pe12 i/o ft pe12 tim1_ch3n k6 - - - 44 - pe13 i/o ft pe13 tim1_ch3 g7 - - - 45 - pe14 i/o ft pe14 tim1_ch4 table 5. medium-density stm32f103xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga100 lqfp48/vfqfpn48 tfbga64 lqfp64 lqfp100 vfqfpn36 default remap
stm32f103x8, stm32f103xb pinouts and pin description doc id 13587 rev 12 29/96 h7 - - - 46 - pe15 i/o ft pe15 tim1_bkin j7 21 g7 29 47 - pb10 i/o ft pb10 i2c2_scl/ usart3_tx (8) tim2_ch3 k7 22 h7 30 48 - pb11 i/o ft pb11 i2c2_sda/ usart3_rx (8) tim2_ch4 e7 23 d6 31 49 18 v ss_1 sv ss_1 f7 24 e6 32 50 19 v dd_1 sv dd_1 k8 25 h8 33 51 - pb12 i/o ft pb12 spi2_nss/ i2c2_smbal/ usart3_ck (8) / tim1_bkin (8) j8 26 g8 34 52 - pb13 i/o ft pb13 spi2_sck/ usart3_cts (8) / tim1_ch1n (8) h8 27 f8 35 53 - pb14 i/o ft pb14 spi2_miso/ usart3_rts (8) tim1_ch2n (8) g8 28 f7 36 54 - pb15 i/o ft pb15 spi2_mosi/ tim1_ch3n (8) k9 - - - 55 - pd8 i/o ft pd8 usart3_tx j9 - - - 56 - pd9 i/o ft pd9 usart3_rx h9 - - - 57 - pd10 i/o ft pd10 usart3_ck g9 - - - 58 - pd11 i/o ft pd11 usart3_cts k10 - - - 59 - pd12 i/o ft pd12 tim4_ch1 / usart3_rts j10 - - - 60 - pd13 i/o ft pd13 tim4_ch2 h10 - - - 61 - pd14 i/o ft pd14 tim4_ch3 g10 - - - 62 - pd15 i/o ft pd15 tim4_ch4 f10 - f6 37 63 - pc6 i/o ft pc6 tim3_ch1 e10 e7 38 64 - pc7 i/o ft pc7 tim3_ch2 f9 e8 39 65 - pc8 i/o ft pc8 tim3_ch3 e9 - d8 40 66 - pc9 i/o ft pc9 tim3_ch4 d9 29 d7 41 67 20 pa8 i/o ft pa8 usart1_ck/ tim1_ch1 (8) /mco table 5. medium-density stm32f103xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga100 lqfp48/vfqfpn48 tfbga64 lqfp64 lqfp100 vfqfpn36 default remap
pinouts and pin description stm32f103x8, stm32f103xb 30/96 doc id 13587 rev 12 c9 30 c7 42 68 21 pa9 i/o ft pa9 usart1_tx (8) / tim1_ch2 (8) d1031c6436922 pa10 i/oft pa10 usart1_rx (8) / tim1_ch3 (8) c1032c8447023 pa11 i/oft pa11 usart1_cts/ canrx (8) / usbdm tim1_ch4 (8) b1033b8457124 pa12 i/oft pa12 usart1_rts/ cantx (8) //usbdp tim1_etr (8) a10 34 a8 46 72 25 pa13 i/o ft jtms/swdio pa13 f8 - - - 73 - not connected e6 35 d5 47 74 26 v ss_2 sv ss_2 f6 36 e5 48 75 27 v dd_2 sv dd_2 a9 37 a7 49 76 28 pa14 i/o ft jtck/swclk pa14 a8 38 a6 50 77 29 pa15 i/o ft jtdi tim2_ch1_etr/ pa 1 5 / s p i 1 _ n s s b9 - b7 51 78 pc10 i/o ft pc10 usart3_tx b8 - b6 52 79 pc11 i/o ft pc11 usart3_rx c8 - c5 53 80 pc12 i/o ft pc12 usart3_ck d8 5 c1 5 81 2 pd0 i/o ft osc_in (9) canrx e8 6 d1 6 82 3 pd1 i/o ft osc_out (9) cantx b7 b5 54 83 - pd2 i/o ft pd2 tim3_etr c7 - - - 84 - pd3 i/o ft pd3 usart2_cts d7 - - - 85 - pd4 i/o ft pd4 usart2_rts b6 - - - 86 - pd5 i/o ft pd5 usart2_tx c6 - - - 87 - pd6 i/o ft pd6 usart2_rx d6 - - - 88 - pd7 i/o ft pd7 usart2_ck a7 39 a5 55 89 30 pb3 i/o ft jtdo tim2_ch2 / pb3 traceswo spi1_sck a6 40 a4 56 90 31 pb4 i/o ft jntrst tim3_ch1/ pb4/ spi1_miso table 5. medium-density stm32f103xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga100 lqfp48/vfqfpn48 tfbga64 lqfp64 lqfp100 vfqfpn36 default remap
stm32f103x8, stm32f103xb pinouts and pin description doc id 13587 rev 12 31/96 c5 41 c4 57 91 32 pb5 i/o pb5 i2c1_smbal tim3_ch2 / spi1_mosi b5 42 d3 58 92 33 pb6 i/o ft pb6 i2c1_scl (8) / tim4_ch1 (8) usart1_tx a5 43 c3 59 93 34 pb7 i/o ft pb7 i2c1_sda (8) / tim4_ch2 (8) usart1_rx d5 44 b4 60 94 35 boot0 i boot0 b4 45 b3 61 95 - pb8 i/o ft pb8 tim4_ch3 (8) i2c1_scl / canrx a4 46 a3 62 96 - pb9 i/o ft pb9 tim4_ch4 (8) i2c1_sda/ cantx d4 - - - 97 - pe0 i/o ft pe0 tim4_etr c4 - - - 98 - pe1 i/o ft pe1 e5 47 d4 63 99 36 v ss_3 sv ss_3 f5 48 e4 64 100 1 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. 3. function availability depends on the chosen device. for devices having reduced peripher al counts, it is always the lower number of peripheral that is included. for example, if a device has only one spi and two usarts, they will be called spi1 and usart1 & usart2, respectively. refer to table 2 on page 10 . 4. if several peripherals share the same i/o pin, to avoid c onflict between these alternate f unctions only one peripheral should be enabled at a time through the peri pheral clock enable bit (in the correspondi ng rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register description sections in the stm32f10xxx reference manual, available from the stmicroelectronics website: www.st.com. 7. unlike in the lqfp64 package, there is no pc3 in the tfbga64 package. the v ref+ functionality is provided instead. 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug configurat ion section in the stm32f10xxx reference manual, available from the stmicroelectroni cs website: www.st.com. 9. the pins number 2 and 3 in the vfqfpn36 package, 5 and 6 in the lqfp48 and lqfp64 packages, and c1 and c2 in the tfbga64 package are configured as osc_ in/osc_out after reset, however t he functionality of pd0 and pd1 can be remapped by software on these pins. for the lqfp100 package , pd0 and pd1 are available by default, so there is no need for remapping. for more details, refer to the alter nate function i/o and debug configuration section in the stm32f10xxx reference manual. the use of pd0 and pd1 in output mode is limited as they can only be used at 50 mhz in output mode. table 5. medium-density stm32f103xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga100 lqfp48/vfqfpn48 tfbga64 lqfp64 lqfp100 vfqfpn36 default remap
memory mapping stm32f103x8, stm32f103xb 32/96 doc id 13587 rev 12 4 memory mapping the memory map is shown in figure 10 . figure 10. memory map reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 0c00 0x4000 2800 0x4000 2c00 0x4000 3000 0x4000 3400 0x4000 3800 0x4000 3c00 0x4000 4400 0x4000 4800 0x4000 4c00 0x4001 0c00 0x4001 1000 0x4001 1400 0x4001 1800 0x4002 1400 apb memory space dma 0x4002 1000 tim2 reserved 0x4001 0800 0x4001 1c00 0x4001 2400 0x4001 2800 0x4001 2c00 0x4001 3000 0x4001 3400 0x4001 3800 tim3 tim4 reserved rtc wwdg iwdg reserved spi2 usart2 usart3 afio port a port c port d rese rve d adc1 reserved usart1 reserved 0x4002 0400 0x4002 0000 0x4001 3c00 0x4000 5400 0x4000 5800 reserved adc2 tim1 spi1 reserved i2c1 bkp 0x4000 6000 0x4000 5c00 por t e pwr port b i2c2 reserved bxcan exti reserved rcc reserved flash interface reserved reserved reserved 0x4000 6400 0x4000 6800 0x4000 6c00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4002 2000 0x4002 2400 0x4002 3000 0x4002 3400 0x6000 0000 0xe010 0000 reserved 0xffff ffff usb reg isters crc 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0x0000 0000 peripherals sram flash memory rese rved rese rved 0x0800 0000 0x0801 ffff 0x1fff f000 0x1fff ffff system memory option bytes 0x1fff f800 0x1fff f80f cortex- m3 internal peripherals 0xe010 0000 ai14394f shared 512 byte usb/can sram aliased to flash or system memory depending on boot pins 0x0000 0000
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 33/96 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ? ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v ? v dd ? 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ? ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 11 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 12 .
electrical characteristics stm32f103x8, stm32f103xb 34/96 doc id 13587 rev 12 5.1.6 power supply scheme figure 13. power supply scheme caution: in figure 13 , the 4.7 f capacitor must be connected to v dd3 . figure 11. pin loading condition s figure 12. pin input voltage ai14141 c = 50 pf stm32f103xx pin ai14142 stm32f103xx pin v in ai14125d v dd 1/2/3/4/5 an alo g: rcs, pll, ... po wer swi tch v bat gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (osc32k,rtc, backup registers) wake-up logic 5 100 nf + 1 4.7 f 1.8-3.6v regulator v ss 1/2/3/4/5 v dda v ref+ v ref- v ssa adc level shifter io logic v dd 10 nf + 1 f v ref 10 nf + 1 f v dd
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 35/96 5.1.7 current con sumption measurement figure 14. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 6: voltage characteristics , table 7: current characteristics , and table 8: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 6. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five volt tolerant pin (2) 2. i inj(pin) must never be exceeded (see table 7: current characteristics ). this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v in max while a negative injection is induced by v in < v ss . v ss ? 0.3 +5.5 input voltage on any other pin (2) v ss ?? 0.3 v dd +0.3 | ? v ddx | variations between different v dd power pins 50 mv |v ssx ?? v ss | variations between all the different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.11: absolute maximum ratings (electrical sensitivity)
electrical characteristics stm32f103x8, stm32f103xb 36/96 doc id 13587 rev 12 5.3 operating conditions 5.3.1 general operating conditions table 7. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . 3. negative injection disturbs the analog performance of the device. see note in section 5.3.17: 12-bit adc characteristics . injected current on nrst pin 5 injected current on hse osc_in and lse osc_in pins 5 injected current on any other pin (4) 4. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (insta ntaneous values). thes e results are based on characterization with ? i inj(pin) maximum current injection on fo ur i/o port pins of the device. 5 ? i inj(pin) (2) total injected current (sum of all i/o and control pins) (4) 25 table 8. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 9. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 2 3.6 v v dda (1) analog operating voltage (adc not used) must be the same potential as v dd (2) 23.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.8 3.6 v
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 37/96 5.3.2 operating conditions at power-up / power-down subject to general operating conditions for t a . table 10. operating conditions at power-up / power-down 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 1 1 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (3) lfbga100 454 mw lqfp100 434 tfbga64 308 lqfp64 444 lqfp48 363 vfqfpn36 1110 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (4) ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (4) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 1. when the adc is used, refer to table 45: adc characteristics . 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 86 ). 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 86 ). table 9. general operating conditions (continued) symbol parameter conditions min max unit symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ?
electrical characteristics stm32f103x8, stm32f103xb 38/96 doc id 13587 rev 12 table 11. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1 2.5 4.5 ms
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 39/96 5.3.4 embedded reference voltage the parameters given in ta bl e 1 2 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 14: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /2, f pclk2 = f hclk the parameters given in ta bl e 1 3 , ta bl e 1 4 and ta bl e 1 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 12. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.20 1.26 v ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/c
electrical characteristics stm32f103x8, stm32f103xb 40/96 doc id 13587 rev 12 table 13. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization , not tested in production. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 50 50.3 ma 48 mhz 36.1 36.2 36 mhz 28.6 28.7 24 mhz 19.9 20.1 16 mhz 14.7 14.9 8 mhz 8.6 8.9 external clock (2) , all peripherals disabled 72 mhz 32.8 32.9 48 mhz 24.4 24.5 36 mhz 19.8 19.9 24 mhz 13.9 14.2 16 mhz 10.7 11 8 mhz 6.8 7.1 table 14. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max, f hclk max. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 48 50 ma 48 mhz 31.5 32 36 mhz 24 25.5 24 mhz 17.5 18 16 mhz 12.5 13 8 mhz 7.5 8 external clock (2) , all peripherals disabled 72 mhz 29 29.5 48 mhz 20.5 21 36 mhz 16 16.5 24 mhz 11.5 12 16 mhz 8.5 9 8 mhz 5.5 6
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 41/96 figure 15. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled figure 16. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled 0 5 10 15 20 25 30 35 40 45 -40 0 25 70 85 105 temperature (c) consumption (ma) 72 mhz 36 mhz 16 mhz 8 mhz 0 5 10 15 20 25 30 -40 0 25 70 85 105 temperature (c) consumption (ma) 72 mhz 36 mhz 16 mhz 8 mhz
electrical characteristics stm32f103x8, stm32f103xb 42/96 doc id 13587 rev 12 table 15. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max , f hclk max with peripherals enabled. unit t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 30 32 ma 48 mhz 20 20.5 36 mhz 15.5 16 24 mhz 11.5 12 16 mhz 8.5 9 8 mhz 5.5 6 external clock (2) , all peripherals disabled 72 mhz 7.5 8 48 mhz 6 6.5 36 mhz 5 5.5 24 mhz 4.5 5 16 mhz 4 4.5 8 mhz 3 4
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 43/96 figure 17. typical current consumption on v bat with rtc on versus temperature at different v bat values table 16. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd /v bat = 2.0 v v dd /v bat = 2.4 v v dd /v bat = 3.3 v t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) - 23.5 24 200 370 a regulator in low power mode, low- speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) - 13.5 14 180 340 supply current in standby mode low-speed internal rc oscillator and independent watchdog on -2.63.4-- low-speed internal rc oscillator on, independent watchdog off -2.43.2-- low-speed internal rc oscillator and independent watchdog off, low- speed oscillator and rtc off -1.7245 i dd_vbat backup domain supply current low-speed oscillator and rtc on 0.9 1.1 1.4 1.9 (2) 2.2 1. typical values are measured at t a = 25 c. 2. based on characterization, not tested in production. 0 0.5 1 1.5 2 2.5 ?40 c 25 c 70 c 8 5 c 105 c temper a t u re (c) con su mption ( a ) 2 v 2.4 v 3 v 3 .6 v a i17 3 51
electrical characteristics stm32f103x8, stm32f103xb 44/96 doc id 13587 rev 12 figure 18. typical current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v and 3.6 v figure 19. typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v 0 50 100 150 200 250 300 -45 25 70 90 110 temperature (c) consumption (a) 3.3 v 3.6 v 0 50 100 150 200 250 300 -40 0 25 70 85 105 temperature (c) consumption (a) 3.3 v 3.6 v
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 45/96 figure 20. typical current consumption in standby mode versus temperature at v dd = 3.3 v and 3.6 v typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load). all peripherals are disabled except if it is explicitly mentioned. the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /4, f pclk 2 = f hclk /2, f adcclk = f pclk2 /4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 ?45 c 25 c 85 c 105 c temperature (c) consumption (a) 3.3 v 3.6 v
electrical characteristics stm32f103x8, stm32f103xb 46/96 doc id 13587 rev 12 table 17. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 36 27 ma 48 mhz 24.2 18.6 36 mhz 19 14.8 24 mhz 12.9 10.1 16 mhz 9.3 7.4 8 mhz 5.5 4.6 4 mhz 3.3 2.8 2 mhz 2.2 1.9 1 mhz 1.6 1.45 500 khz 1.3 1.25 125 khz 1.08 1.06 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 64 mhz 31.4 23.9 ma 48 mhz 23.5 17.9 36 mhz 18.3 14.1 24 mhz 12.2 9.5 16 mhz 8.5 6.8 8 mhz 4.9 4 4 mhz 2.7 2.2 2 mhz 1.6 1.4 1 mhz 1.02 0.9 500 khz 0.73 0.67 125 khz 0.5 0.48
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 47/96 table 18. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 14.4 5.5 ma 48 mhz 9.9 3.9 36 mhz 7.6 3.1 24 mhz 5.3 2.3 16 mhz 3.8 1.8 8 mhz 2.1 1.2 4 mhz 1.6 1.1 2 mhz 1.3 1 1 mhz 1.11 0.98 500 khz 1.04 0.96 125 khz 0.98 0.95 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 64 mhz 12.3 4.4 48 mhz 9.3 3.3 36 mhz 7 2.5 24 mhz 4.8 1.8 16 mhz 3.2 1.2 8 mhz 1.6 0.6 4 mhz 1 0.5 2 mhz 0.72 0.47 1 mhz 0.56 0.44 500 khz 0.49 0.42 125 khz 0.43 0.41
electrical characteristics stm32f103x8, stm32f103xb 48/96 doc id 13587 rev 12 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 1 9 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 6 table 19. peripheral current consumption (1) 1. f hclk = 72 mhz, f apb1 = f hclk /2, f apb2 = f hclk , default prescaler value for each peripheral. peripheral typical consumption at 25 c unit apb1 tim2 1.2 ma tim3 1.2 tim4 0.9 spi2 0.2 usart2 0.35 usart3 0.35 i2c1 0.39 i2c2 0.39 usb 0.65 can 0.72 apb2 gpio a 0.47 ma gpio b 0.47 gpio c 0.47 gpio d 0.47 gpio e 0.47 adc1 (2) 2. specific conditions for adc: f hclk = 56 mhz, f apb1 = f hclk /2, f apb2 = f hclk , f adcclk = f apb2/4 , adon bit in the adc_cr2 register is set to 1. 1.81 adc2 1.78 tim1 1.6 spi1 0.43 usart1 0.85
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 49/96 5.3.6 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 0 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 9 . low-speed external user clock generated from an external source the characteristics given in ta b l e 2 1 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 9 . table 20. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1825mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 16 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5pf ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss ? v in ? v dd 1 a table 21. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50 c in(lse) osc32_in input capacitance (1) 5pf ducy (lse) duty cycle 30 70 % i l osc32_in input leakage current v ss ? v in ? v dd 1 a
electrical characteristics stm32f103x8, stm32f103xb 50/96 doc id 13587 rev 12 figure 21. high-speed external clock source ac timing diagram figure 22. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 2 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai14143 os c _i n exter nal stm32f103xx clo ck so urc e v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel ai14144b osc32_in exter nal stm32f103xx clo ck so urc e v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 51/96 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 23 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 23. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 3 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 22. hse 4-16 mhz oscillator characteristics (1) (2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor 200 k ? c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 ?? 30 pf i 2 hse driving current v dd = 3.3 v, v in =v ss with 30 pf load 1ma g m oscillator transconductance startup 25 ma/v t su(hse (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms ai14145 osc_ou t osc_in f hse c l1 r f stm32f103xx 8 mh z resonator r ext (1) c l2 resonator with integrated capacitors bias controlled gain
electrical characteristics stm32f103x8, stm32f103xb 52/96 doc id 13587 rev 12 note: for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l ? 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 24. typical application with a 32.768 khz crystal 5.3.7 internal clock source characteristics the parameters given in ta bl e 2 4 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 23. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. based on characterization , not tested in production. symbol parameter conditions min typ max unit r f feedback resistor 5 m ? c (2) 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details r s = 30 k ? 15 pf i 2 lse driving current v dd = 3.3 v, v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (4) 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized 3 s ai14146 osc32_ou t osc32_in f lse c l1 r f stm32f103xx 32.768 kh z resonator c l2 resonator with integrated capacitors bias controlled gain
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 53/96 high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in ta b l e 2 6 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . table 24. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibration? available from the st website www.st.com. 1 (3) 3. guaranteed by design, not tested in production. % factory- calibrated (4) 4. based on characterization , not tested in production. t a = ?40 to 105 c ?2 2.5 % t a = ?10 to 85 c ?1.5 2.2 % t a = 0 to 70 c ?1.3 2 % t a = 25 c ?1.1 1.8 % t su(hsi) (4) hsi oscillator startup time 12s i dd(hsi) (4) hsi oscillator power consumption 80 100 a table 25. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 30 40 60 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (3) lsi oscillator power consumption 0.65 1.2 a
electrical characteristics stm32f103x8, stm32f103xb 54/96 doc id 13587 rev 12 5.3.8 pll characteristics the parameters given in ta bl e 2 7 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . 5.3.9 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. table 26. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup even t to the point in which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s table 27. pll characteristics symbol parameter value unit min (1) 1. based on characterization , not tested in production. typ max (1) f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.0 25 mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 72 mhz t lock pll lock time 200 s jitter cycle-to-cycle jitter 300 ps table 28. flash memory characteristics symbol parameter conditions min (1) typ max (1) unit t prog 16-bit programming time t a ??? ?40 to +105 c 40 52.5 70 s t erase page (1 kb) erase time t a ?? ?40 to +105 c 20 40 ms t me mass erase time t a ?? ?40 to +105 c 20 40 ms
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 55/96 table 29. flash memory endurance and data retention 5.3.10 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 3 0 . they are based on the ems levels and classes defined in application note an1709. i dd supply current read mode f hclk = 72 mhz with 2 wait states, v dd = 3.3 v 20 ma write / erase modes f hclk = 72 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v 1. guaranteed by design, not tested in production. symbol parameter conditions value unit min (1) 1. based on characterization , not tested in production. typ max n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 28. flash memory characteristics (continued) symbol parameter conditions min (1) typ max (1) unit
electrical characteristics stm32f103x8, stm32f103xb 56/96 doc id 13587 rev 12 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 30. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, t a ?? +25 c, f hclk ?? 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, t a ?? +25 c, f hclk ?? 72 mhz conforms to iec 61000-4-4 4a table 31. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz 8/72 mhz s emi peak level v dd ?? 3.3 v, t a ?? 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz 12 12 dbv 30 to 130 mhz 22 19 130 mhz to 1ghz 23 29 sae emi level 4 4 -
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 57/96 5.3.11 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. table 32. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c conforming to jesd22-c101 ii 500 table 33. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a
electrical characteristics stm32f103x8, stm32f103xb 58/96 doc id 13587 rev 12 5.3.12 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 3 4 are derived from tests performed under the conditions summarized in ta b l e 9 . all i/os are cmos and ttl compliant. all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 25 and figure 26 for standard i/os, and in figure 27 and figure 28 for 5 v tolerant i/os. table 34. i/o static characteristics symbol parameter conditions min typ max unit v il standard i/o input low level voltage ?0.5 0.28 (v dd ?2)+0.8 v i/o ft (1) input low level voltage ?0.5 0.32 (v dd ?2)+0.75 v ih standard i/o input high level voltage 0.41 (v dd ?2)+1.3 v dd +0.5 i/o ft (1) input high level voltage 0.42 (v dd ?2)+1 5.5 v hys standard io schmitt trigger voltage hysteresis (2) 200 mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) mv i lkg input leakage current (4) v ss ? v in ? v dd standard i/os ? 1 a v in = 5 v i/o ft 3 r pu weak pull-up equivalent resistor (5) v in ?? v ss 30 40 50 k ? r pd weak pull-down equivalent resistor (5) v in ?? v dd 30 40 50 k ? c io i/o pin capacitance 5 pf 1. ft = 5v tolerant. to sustain a voltage higher than v dd +0.5 the internal pull-up/pull- down resistors must be disabled. 2. hysteresis voltage between schmitt trigger switching levels. based on characteriza tion, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) .
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 59/96 figure 25. standard i/o input characteristics - cmos port figure 26. standard i/o input characteristics - ttl port aib 6 $$ 6 )nputrange notguaranteed 6 )( 6 $$ #-/3standardrequirement6 )( 6 $$ 6 )( 6 ), 6 #-/3standardrequirement6 ), 6 $$ 7 ),max 7 )(min 6 $$ 6 ), ai )nputrange notguaranteed 6 )( 6 ), 6 44,requirements 6 )( 6 6 )( 6 $$ 6 ), 6 $$ 44,requirements 6 ), 6 6 $$ 6 7 ),max 7 )(min
electrical characteristics stm32f103x8, stm32f103xb 60/96 doc id 13587 rev 12 figure 27. 5 v tolerant i/o input characteristics - cmos port figure 28. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general-purpose inputs/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 7 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 7 ). 6$$ #-/3standardrequirements6 )( 6 $$ #-/3standardrequirment6 ), 6 $$ 6 )( 6 ), 6 6 $$ 6 )nputrange notguaranteed aib 6 )( 6 $$ 6 ), 6 $$ notguaranteed )nputrange 44,requirement6 )( 6 6 )(
6 $$ 6 ),
6 $$ 44,requirements6 ), 6 6 )( 6 ), 6 6 $$ 6 7 ),max 7 )(min ai
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 61/96 output voltage levels unless otherwise specified, the parameters given in ta bl e 3 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . all i/os are cmos and ttl compliant. table 35. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) 2. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port i io =+ 8ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 v ol (1)(3) 3. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v 1.3 v v oh (2)(3) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 v ol (1)(3) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v 0.4 v v oh (2)(3) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4
electrical characteristics stm32f103x8, stm32f103xb 62/96 doc id 13587 rev 12 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 29 and ta bl e 3 6 , respectively. unless otherwise specified, the parameters given in ta bl e 3 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 36. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bi ts. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex[1:0] bit value (1) symbol parameter conditions min max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 29 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 63/96 figure 29. i/o ac characteristics definition 5.3.13 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 3 4 ). unless otherwise specified, the parameters given in ta bl e 3 7 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) ?? 2/3)t and if the duty cycle is (45-55%) ? 10 % 50% 90% when loaded by 50pf t t r(io)out table 37. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in ?? v ss 30 40 50 k ? v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 ns
electrical characteristics stm32f103x8, stm32f103xb 64/96 doc id 13587 rev 12 figure 30. recommended nrst pin protection 2. the reset network protects t he device against par asitic resets. 3. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 37 . otherwise the reset will not be taken into account by the device. 5.3.14 tim time r characteristics the parameters given in ta bl e 3 8 are guaranteed by design. refer to section 5.3.12: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). a i141 3 2d s tm 3 2f10x r pu nr s t (2) v dd filter intern a l re s et 0.1 f extern a l re s et circ u it (1) table 38. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 72 mhz 13.9 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 036mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 72 mhz 59.6 s
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 65/96 5.3.15 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 3 9 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 9 . the stm32f103xx performance line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 3 9 . refer also to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 39. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be higher than 2 mhz to achieve standard mode i 2 c frequencies. it must be higher than 4 mhz to achieve fast mode i 2 c frequencies. it must be a multiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 ? s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 ? s c b capacitive load for each bus line 400 400 pf
electrical characteristics stm32f103x8, stm32f103xb 66/96 doc id 13587 rev 12 figure 31. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 40. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of ? 5%. for other speed ranges, the tolerance on the achieved speed ? 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k ? 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384 a i141 33 d s t a rt s da 100 4.7k i2c bus 4.7k 100 v dd v dd s tm 3 2f10x s da s cl t f( s da) t r( s da) s cl t h( s ta) t w( s clh) t w( s cll) t su ( s da) t r( s cl) t f( s cl) t h( s da) s t a rt repe a ted s t a rt t su ( s ta) t su ( s to) s top t su ( s to: s ta)
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 67/96 spi interface characteristics unless otherwise specified, the parameters given in ta bl e 4 1 are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 9 . refer to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 41. spi characteristics (1) 1. remapped spi1 characteristics to be determined. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 18 mhz slave mode 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (2) 2. based on characterization , not tested in production. nss setup time slave mode 4t pclk ns t h(nss) (2) nss hold time slave mode 2t pclk t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (2) t su(si) (2) data input setup time master mode 5 slave mode 5 t h(mi) (2) data input hold time master mode 5 t h(si) (2) slave mode 4 t a(so) (2)(3) 3. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3t pclk t dis(so) (2)(4) 4. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (2)(1) data output valid time slave mode (after enable edge) 25 t v(mo) (2)(1) data output valid time master mode (after enable edge) 5 t h(so) (2) data output hold time slave mode (after enable edge) 15 t h(mo) (2) master mode (after enable edge) 2
electrical characteristics stm32f103x8, stm32f103xb 68/96 doc id 13587 rev 12 figure 32. spi timing diagram - slave mode and cpha = 0 figure 33. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 69/96 figure 34. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . usb characteristics the usb interface is usb-if certified (full speed). table 42. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics stm32f103x8, stm32f103xb 70/96 doc id 13587 rev 12 figure 35. usb timings: definition of data signal rise and fall time 5.3.16 can (controller area network) interface refer to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). table 43. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 fu ll-speed electrical specification, the usbdp (d+) pin should be pulled up with a 1.5 k ? resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32f103xx usb functionality is ensured dow n to 2.7 v but not the full usb electrical characteristics which are degr aded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by design, not tested in production. differential input sensitivity i(usbdp, usbdm) 0.2 v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k ? to 3.6 v (5) 5. r l is the load connected on the usb drivers 0.3 v v oh static output level high r l of 15 k ? to v ss (5) 2.8 3.6 table 44. usb: full-speed electrical characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min max unit driver characteristics t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v ai14137 t f differen tial data lines v ss v cr s t r crossover points
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 71/96 5.3.17 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 4 5 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 9 . note: it is recommended to perform a calibration after each power-up. table 45. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 (1) 220 (1) a f adc adc clock frequency 0.6 14 mhz f s (2) sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain (3) conversion voltage range 0 (v ssa or v ref- tied to ground) v ref+ v r ain (2) external input impedance see equation 1 and ta bl e 4 6 for details 50 k ? r adc (2) sampling switch resistance 1 k ? c adc (2) internal sample and hold capacitor 8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 14 mhz 0.214 s 3 (4) 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (4) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. in devices delivered in vfqfpn and lqfp packages, v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . devices that come in the tfbga64 package have a v ref+ pin but no v ref- pin (v ref- is internally connected to v ssa ), see table 5 and figure 6 . 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 45 .
electrical characteristics stm32f103x8, stm32f103xb 72/96 doc id 13587 rev 12 equation 1: r ain max formula: the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 46. r ain max for f adc = 14 mhz (1) 1. based on characterization , not tested in production. t s (cycles) t s (s) r ain max (k ? ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 47. adc accuracy - limited test conditions (1) (2) 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and ? i inj(pin) in section 5.3.12 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k ? , v dda = 3 v to 3.6 v t a = 25 c measurements made after adc calibration 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 r ain t s f adc c adc 2 n2 + ?? ln ? ? ------------------------------------------------------------- - r adc ? ?
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 73/96 figure 36. adc accuracy characteristics table 48. adc accuracy (1) (2) (3) 1. adc dc accuracy values are m easured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency and temperature ranges. 3. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and ? i inj(pin) in section 5.3.12 does not affect the adc accuracy. symbol parameter test conditions typ max (4) 4. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k ? , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal =
electrical characteristics stm32f103x8, stm32f103xb 74/96 doc id 13587 rev 12 figure 37. typical connection diagram using the adc 1. refer to ta b l e 4 5 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 38 or figure 39 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 38. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. ai14150c stm32f103xx v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) 12-bit converter c adc (1) sample and hold adc converter v ref+ (see note 1) stm32f103xx v dda v ssa /v ref? (see note 1) 1 f // 10 nf 1 f // 10 nf ai14388b
stm32f103x8, stm32f103xb electrical characteristics doc id 13587 rev 12 75/96 figure 39. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. 5.3.18 temperature sen sor characteristics v ref+ /v dda stm32f103xx 1 f // 10 nf v ref? /v ssa ai14389 (see note 1) (see note 1) table 49. ts characteristics symbol parameter min typ max unit t l (1) 1. based on characterization , not tested in production. v sense linearity with temperature ? 1 ? 2 c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 (1) voltage at 25 c 1.34 1.43 1.52 v t start (2) 2. guaranteed by design, not tested in production. startup time 4 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s
package characteristics stm32f103x8, stm32f103xb 76/96 doc id 13587 rev 12 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm32f103x8, stm32f103xb package characteristics doc id 13587 rev 12 77/96 1. drawing is not to scale. 2. the back-side pad is not inte rnally connected to the v ss or v dd power pads. 3. there is an exposed die pad on the underside of the vfqfpn package. it should be soldered to the pcb. all leads should also be soldered to the pcb. it is recommended to connect it to v ss . figure 40. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package outline (1) figure 41. recommended footprint (dimensions in mm) (1)(2)(3) seating plane ddd c c a3 a1 a a2 pin # 1 id r = 0.20 zr_me e2 b 19 10 18 27 28 36 19 d2 e d e l 0.30 6.30 0.50 1.00 4.30 4.30 4.80 4.80 4.10 4.10 1 28 9 19 ai14870b 36 27 18 10 0.75 table 50. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 d 5.875 6.000 6.125 0.2313 0.2362 0.2411 d2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 5.875 6.000 6.125 0.2313 0.2362 0.2411 e2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 l 0.350 0.550 0.750 0.0138 0.0217 0.0295 ddd 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103x8, stm32f103xb 78/96 doc id 13587 rev 12 1. drawing is not to scale. 2. the back-side pad is not inte rnally connected to the v ss or v dd power pads. 3. there is an exposed die pad on the underside of the vfqfpn package. it should be soldered to the pcb. all leads should also be soldered to the pcb. it is recommended to connect it to v ss . figure 42. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1) figure 43. recommended footprint (dimensions in mm) (1)(2)(3) s e a ting pl a ne c a 3 a1 a2 a ddd c pin no. 1 id r = 0.20 bottom view 1 4 8 e e l l 12 1 3 d2 b 24 25 b e2 3 6 3 7 e d v0_me 0.50 7.30 0.75 5.80 5.80 6.20 6.20 5.60 5.60 13 1 24 37 ai15799 12 48 36 25 0.55 0.30 0.20 table 51. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 d 6.850 7.000 7.150 0.2697 0.2756 0.2815 d2 2.250 4.700 5.250 0.0886 0.1850 0.2067 e 6.850 7.000 7.150 0.2697 0.2756 0.2815 e2 2.250 4.700 5.250 0.0886 0.1850 0.2067 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f103x8, stm32f103xb package characteristics doc id 13587 rev 12 79/96 figure 44. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package outline 1. drawing is not to scale. table 52. lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.700 0.0669 a1 0.270 0.0106 a2 1.085 0.0427 a3 0.30 0.0118 a4 0.80 0.0315 b 0.45 0.50 0.55 0.0177 0.0197 0.0217 d 9.85 10.00 10.15 0.3878 0.3937 0.3996 d1 7.20 0.2835 e 9.85 10.00 10.15 0.3878 0.3937 0.3996 e1 7.20 0.2835 e 0.80 0.0315 f 1.40 0.0551 ddd 0.12 0.0047 eee 0.15 0.0059 fff 0.08 0.0031 n (number of balls) 100
package characteristics stm32f103x8, stm32f103xb 80/96 doc id 13587 rev 12 figure 45. recommended pcb design rules (0.80/0.75 mm pitch bga) dpad dsm dpad 0.37 mm dsm 0.52 mm typ. (depends on solder mask registration tolerance solder paste 0.37 mm aperture diameter ? non solder mask defined pads are recommended ? 4 to 6 mils screen print
stm32f103x8, stm32f103xb package characteristics doc id 13587 rev 12 81/96 figure 46. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline (1) figure 47. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 table 53. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.6 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 d 15.8 16 16.2 0.622 0.6299 0.6378 d1 13.8 14 14.2 0.5433 0.5512 0.5591 d3 12 0.4724 e 15.8 16 16.2 0.622 0.6299 0.6378 e1 13.8 14 14.2 0.5433 0.5512 0.5591 e3 12 0.4724 e 0.5 0.0197 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103x8, stm32f103xb 82/96 doc id 13587 rev 12 figure 48. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline (1) figure 49. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 54. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 ? 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f103x8, stm32f103xb package characteristics doc id 13587 rev 12 83/96 figure 50. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline 1. drawing is not to scale. table 55. tfbga64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.200 0.0472 a1 0.150 0.0059 a2 0.785 0.0309 a3 0.200 0.0079 a4 0.600 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d1 3.500 0.1378 e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e1 3.500 0.1378 e 0.500 0.0197 f 0.750 0.0295 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 a 3 a4 a2 a1 a s e a ting pl a ne b a d d1 e f f e1 e e h g f e d c b a 12 3 4567 8 a1 ba ll p a d corner ? b (64 ba ll s ) bottom view c me_r 8
package characteristics stm32f103x8, stm32f103xb 84/96 doc id 13587 rev 12 figure 51. recommended pcb design rules for pads (0.5 mm pitch bga) 1. non solder mask defined (nsmd) pads are recommended 2. 4 to 6 mils solder paste screen printing process pitch 0.5 mm d pad 0.27 mm dsm 0.35 mm typ (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter dpad dsm ai15495
stm32f103x8, stm32f103xb package characteristics doc id 13587 rev 12 85/96 figure 52. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package outline (1) figure 53. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 a1 l1 l k c b ccc c a1 a2 a c seating plane 0.25 mm gage plane e3 e1 e 12 13 24 25 48 1 36 37 pin 1 identification 5b_me 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 table 56. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103x8, stm32f103xb 86/96 doc id 13587 rev 12 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 9: general operating conditions on page 36 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ? ja ) where: t a max is the maximum ambient temperature in ? c, ? ja is the package junction-to-ambient thermal resistance, in ? c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 57. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient lfbga100 - 10 10 mm / 0.8 mm pitch 44 c/w thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient tfbga64 - 5 5 mm / 0.5 mm pitch 65 thermal resistance junction-ambient lqfp48 - 7 x 7 mm / 0.5 mm pitch 55 thermal resistance junction-ambient vfqfpn 48 -7 7 mm / 0.5 mm pitch 16 thermal resistance junction-ambient vfqfpn 36 - 6 6 mm / 0.5 mm pitch 18
stm32f103x8, stm32f103xb package characteristics doc id 13587 rev 12 87/96 6.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 58: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 5 7 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 82 c + (46 c/w 447 mw) = 82 c + 20.6 c = 102.6 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see table 58: ordering information scheme ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw
package characteristics stm32f103x8, stm32f103xb 88/96 doc id 13587 rev 12 using the values obtained in ta b l e 5 7 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 115 c + (46 c/w 134 mw) = 115 c + 6.2 c = 121.2 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see table 58: ordering information scheme ). figure 54. lqfp100 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7
stm32f103x8, stm32f103xb ordering information scheme doc id 13587 rev 12 89/96 7 ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 58. ordering information scheme example: stm32 f 103 c 8 t 7 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 103 = performance line pin count t = 36 pins c = 48 pins r = 64 pins v = 100 pins flash memory size (1) 1. although stm32f103x6 devices are not described in this datasheet, or derable part numbers that do not show the a internal code after tem perature range code 6 or 7 should be referred to this datasheet for the electrical characteri stics. the low-density datasheet only cove rs stm32f103x6 devices that feature the a code. 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package h = bga t = lqfp u = vfqfpn temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and real
revision history stm32f103x8, stm32f103xb 90/96 doc id 13587 rev 12 8 revision history table 59. document revision history date revision changes 01-jun-2007 1 initial release. 20-jul-2007 2 flash memory size modified in note 8 , note 5 , note 7 , note 9 and bga100 pins added to table 5: medium-density stm32f103xx pin definitions . figure 3: stm32f103xx performance line lfbga100 ballout added. t hse changed to t lse in figure 22: low-speed external clock source ac timing diagram . v bat ranged modified in power supply schemes . t su(lse) changed to t su(hse) in table 22: hse 4-16 mhz oscillator characteristics . i dd(hsi) max value added to table 24: hsi oscillator characteristics . sample size modified and machine model removed in electrostatic discharge (esd) . number of parts modified and standard reference updated in static latch-up . 25 c and 85 c conditions removed and class name modified in table 33: electrical sensitivities . r pu and r pd min and max values added to table 34: i/o static characteristics . r pu min and max values added to table 37: nrst pin characteristics . figure 31: i 2 c bus ac waveforms and measurement circuit and figure 30: recommended nrst pin protection corrected. notes removed below ta bl e 9 , ta bl e 3 7 , ta b l e 4 3 . i dd typical values changed in table 11: maximum current consumption in run and sleep modes . table 38: timx characteristics modified. t stab , v ref+ value, t lat and f trig added to table 45: adc characteristics . in table 29: flash memory endurance and data retention , typical endurance and data retention for t a = 85 c added, data retention for t a = 25 c removed. v bg changed to v refint in table 12: embedded internal reference voltage . document title changed. controller area network (can) section modified. figure 13: power supply scheme modified. features on page 1 list optimized. small text changes.
stm32f103x8, stm32f103xb revision history doc id 13587 rev 12 91/96 18-oct-2007 3 stm32f103cbt6, stm32f103t6 a nd stm32f103t8 root part numbers added (see table 2: stm32f103xx medium-density device features and peripheral counts ) vfqfpn36 package added (see section 6: package characteristics ). all packages are ecopack? compliant. package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see section 6: package characteristics ). table 5: medium-density stm32f103xx pin definitions updated and clarified. table 26: low-power mode wakeup timings updated. t a min corrected in table 12: embedded internal reference voltage . note 2 added below table 22: hse 4-16 mhz oscillator characteristics . v esd(cdm) value added to table 32: esd absolute maximum ratings . note 3 added and v oh parameter description modified in table 35: output voltage characteristics . note 1 modified under table 36: i/o ac characteristics . equation 1 and ta b l e 4 6 : r ain max for f adc = 14 mhz added to section 5.3.17: 12-bit adc characteristics . v ain , t s max, t conv , v ref+ min and t lat max modified, notes modified and t latr added in table 45: adc characteristics . figure 36: adc accuracy characteristics updated. note 1 modified below figure 37: typical connection diagram using the adc . electrostatic discharge (esd) on page 57 modified. number of tim4 channels modified in figure 1: stm32f103xx performance line block diagram . maximum current consumption ta bl e 1 3 , ta b l e 1 4 and ta b l e 1 5 updated. v hys modified in table 34: i/o static characteristics . table 48: adc accuracy updated. t vdd modified in table 10: operating conditions at power-up / power-down . v fesd value added in ta b l e 3 0 : ems characteristics . values corrected, note 2 modified and note 3 removed in ta bl e 2 6 : low-power mode wakeup timings . table 16: typical and maximum current consumptions in stop and standby modes : typical values added for v dd /v bat = 2.4 v, note 2 modified, note 2 added. table 21: typical current consumption in standby mode added. on-chip peripheral current consumption on page 48 added. acc hsi values updated in table 24: hsi oscillator characteristics . v prog added to table 28: flash memory characteristics . upper option byte address modified in figure 10: memory map . typical f lsi value added in table 25: lsi oscillator characteristics and internal rc value corrected from 32 to 40 khz in entire document. t s_temp added to table 49: ts characteristics . n end modified in table 29: flash memory endurance and data retention . t s_vrefint added to table 12: embedded internal reference voltage . handling of unused pins specified in general input/output characteristics on page 58 . all i/os are cmos and ttl compliant. figure 38: power supply and reference decoupling (v ref+ not connected to v dda ) modified. t jitter and f vco removed from table 27: pll characteristics . appendix a: important notes on page 81 added. added figure 15 , figure 16 , figure 18 and figure 20 . table 59. document revision history (continued) date revision changes
revision history stm32f103x8, stm32f103xb 92/96 doc id 13587 rev 12 22-nov-2007 4 document status promoted from preliminary data to datasheet. the stm32f103xx is usb certified. small text changes. power supply schemes on page 15 modified. number of communication peripherals corrected for stm32f103tx and number of gpios corrected for lqfp package in table 2: stm32f103xx medium- density device features and peripheral counts . main function and default alternate function modified for pc14 and pc15 in, note 6 added and remap column added in table 5: medium- density stm32f103xx pin definitions . v dd ?v ss ratings and note 1 modified in table 6: voltage characteristics , note 1 modified in table 7: current characteristics . note 1 and note 2 added in table 11: embedded reset and power control block characteristics . i dd value at 72 mhz with peripherals enabled modified in ta b l e 1 4 : maximum current consumption in run mode, code with data processing running from ram . i dd value at 72 mhz with peripherals enabled modified in ta b l e 1 5 : maximum current consumption in sleep mode, code running from flash or ram on page 42 . i dd_vbat typical value at 2.4 v modified and i dd_vbat maximum values added in table 16: typical and maximum current consumptions in stop and standby modes . note added in table 17 on page 46 and table 18 on page 47 . adc1 and adc2 consumption and notes modified in table 19: peripheral current consumption . t su(hse) and t su(lse) conditions modified in ta b l e 2 2 and ta b l e 2 3 , respectively. maximum values removed from table 26: low-power mode wakeup timings . t ret conditions modified in table 29: flash memory endurance and data retention . figure 13: power supply scheme corrected. figure 19: typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v added. note removed below figure 32: spi timing diagram - slave mode and cpha = 0 . note added below figure 33: spi timing diagram - slave mode and cpha = 1 (1) . details on unused pins removed from general input/output characteristics on page 58 . table 41: spi characteristics updated. table 42: usb startup time added. v ain , t lat and t latr modified, note added and i lkg removed in table 45: adc characteristics . test conditions modified and note added in table 48: adc accuracy . note added below ta b l e 4 6 and ta b l e 4 9 . inch values corrected in table 53: lqpf100, 14 x 14 mm 100-pin low- profile quad flat package mechanical data , table 54: lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data and table 56: lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . ? ja value for vfqfpn36 package added in table 57: package thermal characteristics ? order codes replaced by section 7: ordering information scheme . mcu ?s operating conditions modified in typical current consumption on page 45 . avg_slope and v 25 modified in ta bl e 4 9 : t s characteristics . i2c interface characteristics on page 65 modified. impedance size specified in a.4: voltage glitch on adc input 0 on page 81 . table 59. document revision history (continued) date revision changes
stm32f103x8, stm32f103xb revision history doc id 13587 rev 12 93/96 14-mar-2008 5 figure 2: clock tree on page 12 added. maximum t j value given in table 8: thermal characteristics on page 36 . crc feature added (see crc (cyclic redundancy check) calculation unit on page 9 and figure 10: memory map on page 32 for address). i dd modified in table 16: typical and maximum current consumptions in stop and standby modes . acc hsi modified in table 24: hsi oscillator characteristics on page 53 , note 2 removed. p d , t a and t j added, t prog values modified and t prog description clarified in table 28: flash memory characteristics on page 54 . t ret modified in table 29: flash memory endurance and data retention . v nf(nrst) unit corrected in table 37: nrst pin characteristics on page 63 . table 41: spi characteristics on page 67 modified. i vref added to table 45: adc characteristics on page 71 . table 47: adc accuracy - limited test conditions added. table 48: adc accuracy modified. lqfp100 package specifications updated (see section 6: package characteristics on page 76 ). recommended lqfp100, lqfp 64, lqfp48 and vfqfpn36 footprints added (see figure 47 , figure 49 , figure 53 and figure 41 ). section 6.2: thermal characteristics on page 86 modified, section 6.2.1 and section 6.2.2 added. appendix a: important notes on page 81 removed. 21-mar-2008 6 small text changes. figure 10: memory map clarified. in table 29: flash memory endurance and data retention : ?n end tested over the whole temperature range ? cycling conditions specified for t ret ?t ret min modified at t a = 55 c v 25 , avg_slope and t l modified in table 49: ts characteristics . crc feature removed. 22-may-2008 7 crc feature added back. small text changes. section 1: introduction modified. section 2.2: full compatibility throughout the family added. i dd at t a max = 105 c added to table 16: typical and maximum current consumptions in stop and standby modes on page 43 . i dd_vbat removed from table 21: typical current consumption in standby mode on page 47 . values added to table 40: scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) on page 66 . figure 32: spi timing diagram - slave mode and cpha = 0 on page 68 modified. equation 1 corrected. t ret at t a = 105 c modified in table 29: flash memory endurance and data retention on page 55 . v usb added to table 43: usb dc electrical characteristics on page 70 . figure 54: lqfp100 p d max vs. t a on page 88 modified. axx option added to table 58: ordering information scheme on page 89 . table 59. document revision history (continued) date revision changes
revision history stm32f103x8, stm32f103xb 94/96 doc id 13587 rev 12 21-jul-2008 8 power supply supervisor updated and v dda added to ta b l e 9 : g e n e r a l operating conditions . capacitance modified in figure 13: power supply scheme on page 34 . table notes revised in section 5: electrical characteristics . table 16: typical and maximum current consumptions in stop and standby modes modified. data added to table 16: typical and maximum current consumptions in stop and standby modes and table 21: typical current consumption in standby mode removed. f hse_ext modified in table 20: high-speed external user clock characteristics on page 49 . f pll_in modified in table 27: pll characteristics on page 54 . minimum sda and scl fall time value for fast mode removed from table 39: i 2 c characteristics on page 65 , note 1 modified. t h(nss) modified in table 41: spi characteristics on page 67 and figure 32: spi timing diagram - slave mode and cpha = 0 on page 68 . c adc modified in table 45: adc characteristics on page 71 and figure 37: typical connection diagram using the adc modified. typical t s_temp value removed from table 49: ts characteristics on page 75 . lqfp48 package specifications updated (see ta b l e 5 6 and ta b l e 5 3 ), section 6: package characteristics revised. axx option removed from table 58: ordering information scheme on page 89 . small text changes. 22-sep-2008 9 stm32f103x6 part numbers removed (see table 58: ordering information scheme ). small text changes. general-purpose timers (timx) and advanced-control timer (tim1) on page 18 updated. notes updated in table 5: medium-density stm32f103xx pin definitions on page 27 . note 2 modified below table 6: voltage characteristics on page 35 , | ? v ddx | min and | ? v ddx | min removed. measurement conditions specified in section 5.3.5: supply current characteristics on page 39 . i dd in standby mode at 85 c modified in table 16: typical and maximum current consumptions in stop and standby modes on page 43 . general input/output characteristics on page 58 modified. f hclk conditions modified in table 30: ems characteristics on page 56 . ? ja and pitch value modified for lfbga100 package in table 57: package thermal characteristics . small text changes. table 59. document revision history (continued) date revision changes
stm32f103x8, stm32f103xb revision history doc id 13587 rev 12 95/96 23-apr-2009 10 i/o information clarified on page 1 . figure 3: stm32f103xx performance line lfbga100 ballout modified. figure 10: memory map modified. table 4: timer feature comparison added. pb4, pb13, pb14, pb15, pb3/traceswo moved from default column to remap column in table 5: medium-density stm32f103xx pin definitions . p d for lfbga100 corrected in table 9: general operating conditions . note modified in table 13: maximum current consumption in run mode, code with data processing running from flash and ta b l e 1 5 : maximum current consumption in sleep mode, code running from flash or ram . table 20: high-speed external user clock characteristics and ta b l e 2 1 : low-speed external user clock characteristics modified. figure 19 shows a typical curve (title modified). acc hsi max values modified in table 24: hsi oscillator characteristics . tfbga64 package added (see ta bl e 5 5 and ta bl e 5 0 ). small text changes. 22-sep-2009 11 note 5 updated and note 4 added in table 5: medium-density stm32f103xx pin definitions . v rerint and t coeff added to table 12: embedded internal reference voltage . i dd_vbat value added to table 16: typical and maximum current consumptions in stop and standby modes . figure 17: typical current consumption on v bat with rtc on versus temperature at different v bat values added. f hse_ext min modified in table 20: high-speed external user clock characteristics . c l1 and c l2 replaced by c in table 22: hse 4-16 mhz oscillator characteristics and table 23: lse oscillator characteristics (f lse = 32.768 khz) , notes modified and moved below the tables. ta b l e 2 4 : h s i oscillator characteristics modified. conditions removed from ta b l e 2 6 : low-power mode wakeup timings . note 1 modified below figure 23: typical application with an 8 mhz crystal . iec 1000 standard updated to iec 61000 and sae j1752/3 updated to iec 61967-2 in section 5.3.10: emc characteristics on page 55 . jitter added to table 27: pll characteristics . table 41: spi characteristics modified. c adc and r ain parameters modified in table 45: adc characteristics . r ain max values modified in table 46: r ain max for f adc = 14 mhz . figure 44: lfbga100 - 10 x 10 mm low profile fine pitch ball grid array package outline updated. 03-jun-2010 12 added stm32f103tb devices. added vfqfpn48 package. updated note 2 below ta bl e 3 9 : i 2 c characteristics updated figure 31: i 2 c bus ac waveforms and measurement circuit updated figure 30: recommended nrst pin protection updated section 5.3.12: i/o port characteristics table 59. document revision history (continued) date revision changes
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